[−][src]Module stm32l4x6::rcc
Reset and clock control
Modules
| ahb1rstr |
AHB1 peripheral reset register |
| ahb1enr |
AHB1 peripheral clock enable register |
| ahb1smenr |
AHB1 peripheral clocks enable in Sleep and Stop modes register |
| ahb2rstr |
AHB2 peripheral reset register |
| ahb2enr |
AHB2 peripheral clock enable register |
| ahb2smenr |
AHB2 peripheral clocks enable in Sleep and Stop modes register |
| ahb3rstr |
AHB3 peripheral reset register |
| ahb3enr |
AHB3 peripheral clock enable register |
| ahb3smenr |
AHB3 peripheral clocks enable in Sleep and Stop modes register |
| apb2rstr |
APB2 peripheral reset register |
| apb2enr |
APB2ENR |
| apb2smenr |
APB2SMENR |
| apb1enr1 |
APB1ENR1 |
| apb1enr2 |
APB1 peripheral clock enable register 2 |
| apb1rstr1 |
APB1 peripheral reset register 1 |
| apb1rstr2 |
APB1 peripheral reset register 2 |
| apb1smenr1 |
APB1SMENR1 |
| apb1smenr2 |
APB1 peripheral clocks enable in Sleep and Stop modes register 2 |
| bdcr |
BDCR |
| ccipr |
CCIPR |
| cfgr |
Clock configuration register |
| cicr |
Clock interrupt clear register |
| cier |
Clock interrupt enable register |
| cifr |
Clock interrupt flag register |
| cr |
Clock control register |
| csr |
CSR |
| icscr |
Internal clock sources calibration register |
| pllcfgr |
PLL configuration register |
| pllsai1cfgr |
PLLSAI1 configuration register |
| pllsai2cfgr |
PLLSAI2 configuration register |
Structs
| AHB1RSTR |
AHB1 peripheral reset register |
| AHB1ENR |
AHB1 peripheral clock enable register |
| AHB1SMENR |
AHB1 peripheral clocks enable in Sleep and Stop modes register |
| AHB2RSTR |
AHB2 peripheral reset register |
| AHB2ENR |
AHB2 peripheral clock enable register |
| AHB2SMENR |
AHB2 peripheral clocks enable in Sleep and Stop modes register |
| AHB3RSTR |
AHB3 peripheral reset register |
| AHB3ENR |
AHB3 peripheral clock enable register |
| AHB3SMENR |
AHB3 peripheral clocks enable in Sleep and Stop modes register |
| APB2RSTR |
APB2 peripheral reset register |
| APB2ENR |
APB2ENR |
| APB2SMENR |
APB2SMENR |
| APB1ENR1 |
APB1ENR1 |
| APB1ENR2 |
APB1 peripheral clock enable register 2 |
| APB1RSTR1 |
APB1 peripheral reset register 1 |
| APB1RSTR2 |
APB1 peripheral reset register 2 |
| APB1SMENR1 |
APB1SMENR1 |
| APB1SMENR2 |
APB1 peripheral clocks enable in Sleep and Stop modes register 2 |
| BDCR |
BDCR |
| CCIPR |
CCIPR |
| CFGR |
Clock configuration register |
| CICR |
Clock interrupt clear register |
| CIER |
Clock interrupt enable register |
| CIFR |
Clock interrupt flag register |
| CR |
Clock control register |
| CSR |
CSR |
| ICSCR |
Internal clock sources calibration register |
| PLLCFGR |
PLL configuration register |
| PLLSAI1CFGR |
PLLSAI1 configuration register |
| PLLSAI2CFGR |
PLLSAI2 configuration register |
| RegisterBlock |
Register block |