1
 2
 3
 4
 5
 6
 7
 8
 9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
//! Base Priority Mask Register (conditional write)

/// Writes to BASEPRI *if*
///
/// - `basepri != 0` AND `basepri::read() == 0`, OR
/// - `basepri != 0` AND `basepri < basepri::read()`
///
/// **IMPORTANT** If you are using a Cortex-M7 device with revision r0p1 you MUST enable the
/// `cm7-r0p1` Cargo feature or this function WILL misbehave.
#[inline]
pub fn write(_basepri: u8) {
    match () {
        #[cfg(all(cortex_m, feature = "inline-asm"))]
        () => unsafe {
            match () {
                #[cfg(not(feature = "cm7-r0p1"))]
                () => asm!("msr BASEPRI_MAX, $0" :: "r"(_basepri) : "memory" : "volatile"),
                #[cfg(feature = "cm7-r0p1")]
                () => ::interrupt::free(
                    |_| asm!("msr BASEPRI_MAX, $0" :: "r"(_basepri) : "memory" : "volatile"),
                ),
            }
        },

        #[cfg(all(cortex_m, not(feature = "inline-asm")))]
        () => unsafe {
            match () {
                #[cfg(not(feature = "cm7-r0p1"))]
                () => {
                    extern "C" {
                        fn __basepri_max(_: u8);
                    }

                    __basepri_max(_basepri)
                }
                #[cfg(feature = "cm7-r0p1")]
                () => {
                    extern "C" {
                        fn __basepri_max_cm7_r0p1(_: u8);
                    }

                    __basepri_max_cm7_r0p1(_basepri)
                }
            }
        },

        #[cfg(not(cortex_m))]
        () => unimplemented!(),
    }
}