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use volatile_register::{RO, RW};
use peripheral::SYST;
#[repr(C)]
pub struct RegisterBlock {
pub csr: RW<u32>,
pub rvr: RW<u32>,
pub cvr: RW<u32>,
pub calib: RO<u32>,
}
#[derive(Clone, Copy, Debug)]
pub enum SystClkSource {
Core,
External,
}
const SYST_COUNTER_MASK: u32 = 0x00ffffff;
const SYST_CSR_ENABLE: u32 = 1 << 0;
const SYST_CSR_TICKINT: u32 = 1 << 1;
const SYST_CSR_CLKSOURCE: u32 = 1 << 2;
const SYST_CSR_COUNTFLAG: u32 = 1 << 16;
const SYST_CALIB_SKEW: u32 = 1 << 30;
const SYST_CALIB_NOREF: u32 = 1 << 31;
impl SYST {
pub fn clear_current(&mut self) {
unsafe { self.cvr.write(0) }
}
pub fn disable_counter(&mut self) {
unsafe { self.csr.modify(|v| v & !SYST_CSR_ENABLE) }
}
pub fn disable_interrupt(&mut self) {
unsafe { self.csr.modify(|v| v & !SYST_CSR_TICKINT) }
}
pub fn enable_counter(&mut self) {
unsafe { self.csr.modify(|v| v | SYST_CSR_ENABLE) }
}
pub fn enable_interrupt(&mut self) {
unsafe { self.csr.modify(|v| v | SYST_CSR_TICKINT) }
}
pub fn get_clock_source(&mut self) -> SystClkSource {
let clk_source_bit = self.csr.read() & SYST_CSR_CLKSOURCE != 0;
match clk_source_bit {
false => SystClkSource::External,
true => SystClkSource::Core,
}
}
pub fn get_current() -> u32 {
unsafe { (*Self::ptr()).cvr.read() }
}
pub fn get_reload() -> u32 {
unsafe { (*Self::ptr()).rvr.read() }
}
pub fn get_ticks_per_10ms() -> u32 {
unsafe { (*Self::ptr()).calib.read() & SYST_COUNTER_MASK }
}
pub fn has_reference_clock() -> bool {
unsafe { (*Self::ptr()).calib.read() & SYST_CALIB_NOREF == 0 }
}
pub fn has_wrapped(&mut self) -> bool {
self.csr.read() & SYST_CSR_COUNTFLAG != 0
}
pub fn is_counter_enabled(&mut self) -> bool {
self.csr.read() & SYST_CSR_ENABLE != 0
}
pub fn is_interrupt_enabled(&mut self) -> bool {
self.csr.read() & SYST_CSR_TICKINT != 0
}
pub fn is_precise() -> bool {
unsafe { (*Self::ptr()).calib.read() & SYST_CALIB_SKEW == 0 }
}
pub fn set_clock_source(&mut self, clk_source: SystClkSource) {
match clk_source {
SystClkSource::External => unsafe { self.csr.modify(|v| v & !SYST_CSR_CLKSOURCE) },
SystClkSource::Core => unsafe { self.csr.modify(|v| v | SYST_CSR_CLKSOURCE) },
}
}
pub fn set_reload(&mut self, value: u32) {
unsafe { self.rvr.write(value) }
}
}